Generally speaking, in a memory read operation, at the active clock edge, internal clock signals are generated, a self time track is activated, a bit line pre-charge signal is disabled, and input addresses are latched. Once decoded, a word line is turned on and bit lines are matured while the word line is selected. Discharge of a self timed bit line will generate a RESET signal, which is used to reset the internal clock, and consequently enable a sense amplifier, disable the word line, and activate bit line pre-charge. The enabled bit line sense amplifier senses from the matured bit line a differential voltage and passes the read data to a data latch and output buffer.
It is important to obtain a proper sense margin (i.e., differential voltage). If the sense margin is too small, i.e., the bit line maturing time is too short because the self timed interval is not long enough, the sense amplifier may not be able to accurately ascertain a data value stored in an accessed memory cell. Thus, the bit lines must mature for a long enough period to achieve a minimum bit line voltage differential. On the other hand, if the maturing time is longer than necessary, power is wasted, as the bit lines continue charging even after the desired bit line voltage differential has been obtained.
The sense timing should be optimized to obtain a proper setup time. If the sensing is delayed too much, the setup time will be delayed. So for fast memory, it is preferred to start the sense enable time as early in the cycle as possible. As noted above, however, a problem with sensing early is that the sense margin will be smaller, potentially causing problems in process variations.
The situation is further complicated in compiler memory, as different size memories will have different optimal bit line maturing times. For small size memory, the signal propagation delay is very short. Accordingly, as soon as the word line rises the bit line will mature quickly and sensing can start earlier. For large memory the bit line capacitance will be larger, and the bit line will mature more slowly. Thus, sensing must wait until after a longer propagation delay.
Because of the different optimal sense times in different size memories, it is important to track the bit line and word line properly. Moreover, as technology scales down and devices become smaller, there are significant process variations in memory bit cells. Tracking memory internal timing to guarantee both high performance and high yield becomes a challenge.
Often, a simulation, such as a Monte Carlo simulation, is performed to determine how much sense margin occurs in a specific process. Based upon the simulation results, a sense enable time can be estimated for various memory sizes. Simulations, however, have drawbacks in that they do not account for real world conditions. Thus, it is preferable to actually track delay to determine sense margins.
A conventional bit line tracking scheme is illustrated in FIGS. 1 and 2. FIG. 1 is a block diagram of a prior art memory, including a memory array 110, a control block 120, a pre-decoder 130, a row decoder and word line driver 140, and a dummy word line driver 150. Also provided are sense amplifiers 160 and a data output buffer 170. The memory array 110 includes a dummy word line DWL, and a dummy column having a dummy bit line DBL and dummy bit line bar DBLB, as well as a dummy bit cell 112. Word lines WL[n]-WL[0] are provided. The memory array 110 also includes numerous bit cells 114, bit lines BL and bit line bars BLB, only one of each being depicted. Programmable dummy pull down devices 116 are also provided. The programmable dummy pull down devices 116 have the same characteristics as the real bit cells 114.
The word lines WL[n]-WL[0] receive an internal clock signal ICLK from the control block, after a six gate delay. The six gate delay results from the internal clock signal ICLK passing through the pre-decoder 130 (two gate delay) and the row decoder and word line driver 140 (four gate delay). In order to track the word lines WL[n]-WL[0], the dummy word line driver 150 is also provided with a four gate delay. This delay is to ensure the dummy word line DWL receives the internal clock signal ICLK at the same time as the word lines WL[n]-WL[0].
FIG. 2 shows a timing diagram for a prior art bit line tracking scheme. An internal clock signal is represented by ICLK. WL represents a word line signal. A bit line and dummy bit line are represented by BL and DBL, respectively. A dummy word line signal is represented by DWL. Sense enable corresponds to a sense enable signal.
For a dummy bit line to track a bit line maturing time tb1 needed to achieve a desired bit line voltage differential ΔVb1, dummy bit line and dummy word line are both asserted at a real word line rising time. Thus, the real word line and dummy word line go high at the same time t1, in response to the internal clock signal ICLK rising.
The dummy bit line DBL will mature faster than the real bit line BL, usually 3-5 times faster, because a delay g1 is necessary between the time when the dummy bit line DBL is determined to be mature and the start of sensing. Such delay g1 is necessary to drive the sense enable signal and also to allow enough time for decoding of the sense enable signal by a column multiplexer. A drawback of the faster maturing time of the dummy bit line DBL is that the dummy bit line DBL does not really approximate the real maturing time of the real bit line BL, reducing tracking accuracy. Moreover, the bit line maturing time tb1 can not be tracked very well by the self timing loop across process-voltage-temperature (PVT) corners.
Based upon desired voltage differential of the dummy bit line ΔVdb1, at time tdb1 plus the gate delay g1 after time t1 a sense enable signal is asserted. Such timing should coincide with the bit line maturing time tb1. However, the gate delay g1 must be appropriately set to ensure the sense enable time is not too early, i.e., before the bit line BL is mature. The setting of the gate delay g1 timing is difficult, especially when the dummy bit line DBL does not mature at the same rate as the real bit line BL. Thus, extra time is usually inserted in the gate delay g1, to ensure the bit line BL has actually matured. Of course, the extra delay means the sense enable time is not immediately after the bit line BL has matured, but rather is a safe period afterwards.
Another problem is that the word line gating time is controlled by the sense enable time. After the sense enable signal goes to low, the word line WL is gated. The sense enable timing is delayed a default time (gate delay g1) after tdb1. From the sense enable time there are additional gate delays to de-assertion of the word line WL, resulting in the bit line BL continuing to charge. In other words, even after the actual bit line sensing, the word line remains asserted. Consequently, power is wasted.